Hi, I'm Ramshankar

Crafting next-generation AI solutions with a focus on Large Language Models, Computer Vision, and GPU Kernel Optimization. I graduated!

Ramshankar Bhuvaneswaran - Portrait

01. Who I Am

I'm a passionate AI/ML Engineer and Researcher recently graduated from Northeastern University with a Master's in Information Systems. My journey in technology began with a deep fascination for artificial intelligence and its potential to solve complex real-world problems.

With a strong foundation in computer science and extensive experience in machine learning, I specialize in developing innovative AI solutions, optimizing ML pipelines, and building scalable data systems. My work spans across computer vision, natural language processing, and distributed computing, with a particular focus on large language models and compiler integrations.

I believe in the power of open-source collaboration. I recently contributed to the LLVM project by refactoring the `ilogbf128` math function to a header-only implementation in libc ( LLVM libc open-source contribution ).

Core Expertise

GPU Kernel Optimization

Developed and optimized high-performance GPU kernels for inference/training workloads, demonstrating deep knowledge of memory hierarchy.

Compiler Integration

Worked with graph compilers (CUDA, HIP) to optimize deep learning frameworks for various hardware architectures including AMD GPUs.

Performance & Cost Resolution

Identified redundant model calls; architected caching systems reducing monthly GPU costs by $12K and latency by 42%.

Technical Skills

Languages

C++ Python CUDA HIP Triton C SQL PySpark R Shell

ML & Frameworks

PyTorch TensorFlow JAX Hugging Face TRL Unsloth vLLM Scikit-learn XGBoost

Cloud & Scale

AWS GCP Docker Kubernetes HPC Multi-GPU SageMaker Vertex AI

02. Experience & Education

GPU Kernel Engineer

Parsewave

Present
  • Designing, implementing, and optimizing CUDA compute kernels.
  • Validating, testing, and benchmarking kernel implementations for correctness and performance.
  • Reviewing CUDA-code datasets and related submissions, assessing correctness, quality, and performance against applicable criteria.
  • Collaborating with the engineering team on related GPU and compute tasks as needed.

AI Engineer

Community Dream Foundation

Remote Apr 2026 – Present
  • Shipped an LLM-powered concierge and operations assistant for a hotel client, building agent workflows in LangChain and LangGraph on vLLM behind FastAPI, with RAG over property data (room inventory, policies, local guides).
  • Wired up custom Skills and MCP connectors to the hotel's booking system, PMS, and internal knowledge base over REST APIs, so the agent could execute transactional operations.
  • Built an evaluation harness with curated guest-query sets and regression checks on prompt changes.

Graduate Teaching and Research Assistant

Northeastern University

Boston, MA Jan 2025 – Dec 2025
  • Implemented a knowledge distillation pipeline compressing a Qwen image-to-image model into lightweight GAN architectures, achieving a 65% parameter reduction while maintaining visual quality.
  • Authored the research paper BitSkip investigating compositional effects of quantization and early exit in Large Language Models.
  • Served as a Teaching Assistant, mentoring students on distributed computing workflows including SLURM job scheduling and parallel processing across CPU and GPU environments.

Master of Science in Information Systems

Northeastern University

Boston, MA 2023 - 2025

Specializing in AI/ML, Data Engineering, and Distributed Systems. Focus on large language models, computer vision, and scalable data processing platforms.

Master's Thesis:

"ModelOpt: Research Framework for Zero-Shot Computer Vision Model Optimization With Tree Search and Federated Knowledge Sharing, Northeastern University, 2025."

AI Engineer

BulkBeings

Chennai, India May 2024 – Aug 2024
  • Optimized PyTorch training pipelines for Mixtral and Llama models, achieving a 42% training acceleration across 8 A100 GPUs FSDP configuration through memory coalescing and kernel fusion.
  • Designed and scaled ML cluster orchestration using Kubernetes and Ray for distributed training, managing GPU scheduling and resource allocation.
  • Engineered high-performance GPU kernels for attention mechanisms and feedforward layers using CUDA (CUTLASS); reduced OOM errors by 85% through systematic memory profiling.

ML Engineer (Research)

BulkBeings

Chennai, India May 2023 – Dec 2023
  • Prototyped OCR model (ViT+CRNN) achieving 98% precision and 42% faster inference via ONNX/CUDA optimization, meeting sub-100ms P99 latency.
  • Implemented an observability stack with Prometheus, Grafana, and OpenTelemetry to track model throughput, latency and GPU utilization.
  • Developed a two-stage Conv1D-Transformer for beat-level ECG classification (89% F1-score) deployed on an L4 GPU.

Bachelor of Technology in Computer Science

Anna University

Chennai, India 2019 - 2023

Comprehensive foundation in computer science fundamentals, data structures, algorithms, and software engineering. Graduated with distinction.

ML Engineer Intern

Velozity Global Solutions Pvt

Chennai, India Jan 2022 – Aug 2022
  • Architected end-to-end ML pipelines in AWS, implementing predictive segments using XGBoost on behavioral patterns, resulting in a 45% increase in campaign conversions.
  • Redesigned temporal feature extraction logic to prevent temporal data leakage, ensuring robust temporal train-test splits.
  • Collaborated on developing retail mix optimization systems using Bayesian hierarchical models (PyMC3), increasing LTV prediction accuracy by 34%.

03. Technical Projects

AMD-GPU-Kernel Agent Trained via GRPO Using verl

SkyPilot verl FastAPI Redis
  • Trained Qwen2.5-Coder-7B via GRPO using verl to autonomously optimize GPU kernels across NVIDIA and AMD targets, achieving rewards up to 4.0x speedup for FP8 classes.
  • Architected a three-cluster SkyPilot pipeline decoupling trainer, queue (FastAPI + Redis) and spot GPU workers, enabling fault-tolerant spot preemption handling.
Repository

Parallelizing Text-to-Image Generation Using Diffusion

Python PyTorch Dask CLIP
  • Built DDPM model from scratch and engineered a Dask-powered distributed preprocessing pipeline for image datasets, achieving 1.48x CPU throughput scaling.
  • Accelerated training via Automatic Mixed Precision (AMP) with Exponential Moving Average (EMA) weight averaging, reducing training time by 11% and loss variance by 29%.
Repository

NVIDIA GB200 GPU Programming Challenge

CuteDSL CUDA PTX Blackwell FP4

Ranked 24th place in GPUMODE's NVFP4 Gated Dual GEMM competition. Optimized Blackwell B200 tensor core kernels for block-scaled matrix operations using CuteDSL and inline PTX assembly, achieving 3-6x speedup over baseline through SwiGLU epilogues and TMA memory pipelining.

Llama3 - Pure C/CUDA Implementation

C/CUDA llm.c Optimization RoPE

An implementation of Llama 3.1 in pure C/CUDA built on Karpathy's llm.c. Optimized various kernels including RMSNorm (yielding 2.3x speedup), SwiGLU with bfloat16, and coalesced memory access, supporting complete forward and backward passes with attention mechanisms.

Repository

Qwen600 CUDA to ROCm Port for AMD MI300X

C++ HIP ROCm AMD MI300X

Ported six essential transformer kernels from NVIDIA CUDA to AMD ROCm/HIP, optimizing for MI300X architecture. Achieved 12.1ms per token generation with 79-83% memory bandwidth utilization, implementing BFloat16 coalesced memory access and reducing memory traffic by 50%.

Advanced Suicidal Ideation Classification System

AWS SageMaker ETL SFT-DPO Sharding

Led development of a multi-conversation classification system to detect mental health risks. Created comprehensive ETL pipelines for 123K samples, implemented hybrid SFT-DPO training, and deployed on SageMaker. Achieved 71% macro-AUC and 40% output consistency improvements.

Two-Stage Cardiac Arrhythmia Detection System

PyTorch Transformer Signal Processing

Designed a CNN-Transformer neural architecture processing ECG signals. First stage classifies overall rhythm patterns with 94-98% accuracy; second stage provides adaptive ectopic beat detection with 90-95% accuracy, featuring dynamic patient-specific rate windowing.

OCR Pipeline with Layout Detection

PyTorch ONNX CUDA Kernels

Deep learning-based OCR system for complex financial documents using ViT + CRNN architectures, achieving 98% text extraction accuracy and 42% faster processing through ONNX runtime and custom CUDA kernel optimization.

Fintech Data Processing ETL Platform

Python Snowflake Airflow FastAPI
  • Built a master financial database for US public companies implementing raw, transformed, and denormalizedfact table schemas to optimize access.
  • Engineered automated SEC ETL pipelines with Airflow, retrieving filings via scrapers and using S3/Snowflake staging with data validation validation checks.
Repository

Medical Knowledge Graph RAG System

Neo4j LangChain Graph RAG Python

Developed a Graph RAG framework for complex medical data retrieval using automated medical triplet extraction and dynamic knowledge graph construction with Neo4j. The system integrates semantic search optimization via LangChain, providing contextual medical answers.

Repository

Stock Price Forecaster

Streamlit HMM Time Series Python

Streamlit application forecasting stock prices using multivariate Hidden Markov Models, capturing opening/closing price differentials and volume triggers. Deployed live with Akaike Information Criterion parameters optimization to prevent state overfitting.

Repository

04. Latest Insights

Featured Article

How I Customized Llama 3.1 8B on a Budget

Democratizing AI: Fine-tuning Large Language Models with Limited Resources.

Fine-tuned large language models consistently outperform generic retrieval-augmented systems. In this article, I document a detailed, step-by-step roadmap to fine-tuning Meta's open-source Llama 3.1 8B parameter model using LoRA adapters, quantization techniques, and budget cloud resources.

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GPU MODE NVFP4 Blackwell Challenge

Mar 13, 2026

The unfiltered worklog of tackling nvfp4_gemm, nvfp4_dual_gemm, and nvfp4_group_gemm challenges — from MLIR serialization errors to PTX-optimized SwiGLU epilogues.

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AMD FlyDSL — competes with CuTe/Cutlass?

Mar 4, 2026

Comparing NVIDIA CuTile and AMD FlyDSL MLIR-based tile programming frameworks by porting a fused MoE kernel and analyzing the generated IR.

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Optimizing LLMs on AMD MI300X

Jan 2025

A deep dive into porting transformer kernels from NVIDIA CUDA to AMD ROCm/HIP, achieving 12.1ms token generation with 83% memory bandwidth.

Read Substack

05. Get In Touch

Let's Connect

I'm open to discussing technical challenges, HPC research collaborations, or compiler engineering opportunities. Reach out!

Phone (857) 693-4328
Location Boston, MA

Schedule Synchronously

Book a direct meeting to align, share technical feedback, or discuss roles.

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